How to test large ASIC or FPGA design flow issues

For smaller FPGAs, systematic bugs resulting from the RTL code refinement process are relatively uncommon and would be discovered durin...



For smaller FPGAs, systematic bugs resulting from the RTL code refinement process are relatively uncommon and would be discovered during the final test of the FPGA within the hardware. 
  For larger FPGAs leveraging modern design flows, this assumption has been proven to be flawed and can lead to significant design problems.



 Figure 1.

Two types of hardware bug can be introduced into ICs, including FPGAs. 
  •  Design bugs through human error are eliminated during functional verification. 
  • Systematic issues, on the other hand, are introduced by the automated design refinement tool chain and typically are not checked by the functional verification process. 

These [two] can be hard to detect and damaging if they make it into the final device.

High-quality FPGA solutions rely on tool chain effectiveness, particularly optimizations provided by synthesis and place and route (P&R) functions. The ratio of registers to available inter-register logic is fixed, allowing sections of the matrix to be wasted if this ratio is unbalanced across the design code. As such, sequential optimizations, where the positions of flip-flops are changed relative to the logical gates, are an important FPGA synthesis and P&R capability (Figure 1).

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