"Testing the Test Bench" - UVM - Universal Verification Methodology

The Universal Verification Methodology (UVM) is a standardized hybrid methodology for verifying complex design in the semiconductor i...

The Universal Verification Methodology (UVM) is a standardized hybrid methodology for verifying complex design in the semiconductor industry. It has superseded the Open Verification Methodology which was an Open Source verification methodology was supported by both Cadence and Mentor. UVM has full industry-wide support and standardized under the Accellera Systems Initiative. In this article, we describe in detail the differences between the Open Verification Methodology (version2.1.2) and the Universal Verification Methodology (version 1.b). It is intended to help engineers to understand the implications of moving from OVM to UVM.

Advantages of UVM

 

UVM (Universal Verification Methodology) is a standardized methodology for verifying the both complex & simple digital design in simple way.

UVM Features:

• First methodology & second collection of class libraries for Automation
• Reusability through testbench
• Plug & Play of verification IPs
• Generic Testbench Development
• Vendor & Simulator Independent
• Smart Testbench i.e. generate legal stimulus as from pre-planned coverage plan
• Support CDV –Coverage Driven Verification
• Support CRV –Constraint Random Verification
• UVM standardized under the Accellera System Initiative
• Register modeling
• Always tied to a given hardware(DUT Interface) Or a TLM port 
• Having phasing mechanism for control the behavior of simulation 
• Configuration Component Topology